Specifications
Process node, operating conditions, crypto throughput, interfaces, package, and power — the engineering numbers for Bastionchip HSM silicon.
BC1-HSM silicon — preliminary datasheet
Pre-production specifications for the Bastionchip BC1-HSM discrete security element. Values reflect first-silicon target; subject to characterization update. Full production datasheet available under NDA.
| Process & Die | ||
|---|---|---|
| Process node | 28 nm FD-SOI | TSMC N28FDS |
| Die area | ~12 mm² | Preliminary estimate |
| Transistor count | ~280 M | Preliminary estimate |
| Package | 64-pin QFP (9×9 mm), 144-ball BGA (10×10 mm) | Two package options |
| Power | ||
| Core supply | 1.0 V ±5% | FD-SOI 28 nm core rail |
| I/O supply | 1.8 V / 3.3 V (selectable) | I/O ring voltage |
| Active power (full AES load) | <250 mW | Target at TJ = 25°C |
| Standby power (mesh armed) | <5 μW | Keys retained, mesh active |
| Zeroize power spike | <10 mW / 2 ns | Energy = <20 pJ |
| Temperature | ||
| Commercial grade | 0°C to +70°C (Tj) | Standard commercial |
| Industrial grade | −40°C to +85°C (Tj) | Defense / embedded OEM |
| Storage temperature | −55°C to +125°C | |
| Crypto Engine Throughput | ||
| AES-256-GCM | 10 Gbps | Dedicated hardware pipeline |
| AES-256-CBC / CTR | 12 Gbps | No authentication overhead |
| SHA-3-256 | 6 Gbps | Keccak hardware core |
| SHA-3-512 | 3 Gbps | |
| HMAC-SHA256 | 8 Gbps | SHA-256 + HMAC wrapper |
| ECDSA P-384 sign | ~2,400 ops/s | Hardware scalar multiplier |
| ECDSA P-384 verify | ~4,800 ops/s | |
| Kyber-768 encapsulate | ~8,000 ops/s | CRYSTALS-Kyber hardware |
| Kyber-768 decapsulate | ~7,500 ops/s | |
| Dilithium-3 sign | ~3,000 ops/s | CRYSTALS-Dilithium hardware |
| True RNG (NIST SP 800-90B) | 800 Mbps | Ring oscillator entropy source |
| Key Storage | ||
| Hardware-protected key slots | 128 slots | 256-bit each; AES or ECC |
| PUF root key | 256 bits | Derived, never stored |
| NVM key backup | AES-256 wrapped by PUF key | On-die NVM; encrypted at rest |
| Key wrapping | AES-256 key wrap (RFC 3394) | For export to host under NDA |
| Physical Security | ||
| Tamper mesh layer count | 3 active metal layers | All over sensitive logic |
| Tamper detection response | <1 ns | Zeroize signal latency |
| Voltage glitch detection | ±5% from nominal | Per-rail monitor |
| Clock glitch detection | Frequency deviation >15% | PLL-based monitor |
| Temperature sensor | Alerts below −40°C / above +100°C | On-die thermal monitor |
| Host Interfaces | ||
| PCIe | Gen 4 × 4 (16 GT/s) | Native endpoint; UEFI driver support |
| SPI | Up to 50 MHz; SPI Mode 0/3 | Embedded / low-speed host |
| I²C | Fast-mode Plus (1 MHz) | Management / config channel |
| USB 2.0 | Full-speed / Hi-speed device | Optional; evaluation kit |
| GPIO / IRQ | 8 bidirectional; 2 IRQ outputs | Tamper alert + status |
| Certification Targets | ||
| FIPS 140-3 | Level 3 (target) | Submission planned post-first-silicon characterization |
| Common Criteria | EAL 4+ (target) | Protection profile: PP-MODULE for HSM |
| PCI-HSM | v3.0 design alignment | Not yet submitted |
All specifications are preliminary design targets. Actual performance verified post-silicon characterization. Certification statuses are targets — no current certifications claimed.
Evaluation program and part numbers
PCIe evaluation board, 1× BC1-HSM silicon sample, test vector package, driver source, and preliminary architecture documentation. NDA required.
Request Eval KitBC1-HSM-C (commercial temp, QFP-64) and BC1-HSM-I (industrial temp, BGA-144). Minimum order and pricing via design-win program.
Contact for Volume PricingFull production datasheet, register map, tamper characterization data, and side-channel test report. Available under mutual NDA to qualified design partners.
Initiate NDAReady to evaluate?
Evaluation kits available for qualified cloud, financial services, and defense design partners. NDA required for full datasheet.