Ex-embedded security, silicon design, and applied cryptography. A small team doing deep work on hardware security silicon in San Jose, CA.
Noam Bar-Lev spent nearly a decade at embedded systems and semiconductor companies in the San Jose–Santa Clara corridor, working on trust architectures and security silicon integration for storage, communications, and embedded platforms. He founded Bastionchip in 2024 after observing that cloud security teams building FIPS 140-3 key custody had no option between a network HSM appliance and a custom chip program — a gap Bastionchip is built to close.
Dae-Won leads RTL design and physical implementation for Bastionchip silicon. His background includes front-end and back-end design on custom security processor cores at embedded systems companies in the San Jose area — from RTL specification through place-and-route closure. At Bastionchip he owns the crypto engine pipeline, tamper mesh controller, and PUF interface RTL.
Priya owns the security threat model and attack surface analysis for Bastionchip silicon, translating adversary capabilities into RTL design constraints. Her background includes applied cryptography research and hardware security evaluation — she has worked on both sides of the FIPS 140-3 boundary, which informs how she structures certification path planning and side-channel countermeasure requirements for the team.
Marcus manages design-win partnerships across cloud infrastructure and financial services, guiding qualified engineering teams through the evaluation program from NDA initiation to first silicon delivery. He focuses on programs where FIPS 140-3 or PCI-HSM requirements are driving the procurement decision — teams that need hardware-rooted key custody and have exhausted network HSM appliance options.
Yuki runs silicon characterization and validation for Bastionchip first-silicon samples — test vector generation, ATE bench setup, crypto throughput profiling, tamper-response timing measurement, and differential power analysis traces that will feed certification submissions. Every evaluation kit shipped to a design partner has been characterized against the published security model before it leaves the lab.
We're looking for RTL design engineers, security architects, and silicon validation engineers. Deep work, small team, San Jose lab.