We build the silicon layer that makes digital trust unconditional
Bastionchip designs purpose-built hardware security silicon for cloud infrastructure, financial services, and defense OEM platforms.
Hardware-rooted trust, available to the ecosystem
To make hardware-rooted cryptographic trust available across the computing ecosystem — not just to hyperscalers with custom silicon programs.
Noam Bar-Lev spent nearly a decade on security silicon and embedded trust architectures at semiconductor and embedded systems companies in the San Jose–Santa Clara corridor before co-founding Bastionchip in 2024. The catalyzing observation came while reviewing the key management architecture for a cloud storage platform: the security team had spent months building policy controls around a software KMS, then realized the host hypervisor could observe every key operation regardless of policy. The only credible fix was hardware — and the only hardware options were a $40,000 network HSM appliance or a custom chip program that required a nine-figure NRE budget.
Bastionchip is building the middle layer that does not yet exist: a discrete silicon component at PCIe and SPI form factor that delivers HSM-grade physical security, PUF-rooted device identity, and hardware attestation — without requiring a custom chip program or a rack-mounted appliance. The same trust guarantee that hyperscalers achieve with custom silicon, available as a BOM component.
Why hardware beats software for root-of-trust
Hardware First
We are not a software HSM, not an FPGA security evaluation board, and not a TPM wrapper. We design purpose-built ASIC silicon where the security properties are enforced in CMOS — not in firmware that can be patched, and not in a trust model that requires the hypervisor to be honest.
Spec Transparency
Security claims require evidence. We publish architecture details, target certifications, and test methodologies openly. NDA-gated datasheets go further — full register maps, tamper characterization data, and side-channel test reports.
Ecosystem Fit
Standard PCIe x4, SPI, and I²C interfaces. Linux 5.15+ kernel driver support. Documented integration profiles for cloud host and embedded OEM PCB. Security silicon that actually ships in products.
Ex-embedded security, silicon design, and applied cryptography
Evaluation partnerships and careers
We're five engineers in a San Jose hardware lab working on first silicon. Evaluation kits for qualified cloud, financial services, and defense programs. Open roles for RTL designers, security architects, and silicon validation engineers who want to work at the boundary between cryptography and CMOS.