Discrete security element with dedicated crypto engine, active tamper-detection mesh, and internal key storage that never traverses external buses.
| Parameter | Value |
|---|---|
| Process node | 28 nm HPC (high-performance CMOS) |
| Die size (target) | 4.2 mm × 4.2 mm |
| Supply voltage | 1.0 V core / 1.8 V I/O |
| Operating temp | −40°C to +85°C (industrial grade) |
| AES-256-GCM throughput | 10 Gbps (hardware pipeline) |
| SHA-3/512 throughput | 5 Gbps |
| ECDSA P-384 ops | 12,000 sign/verify per second |
| Kyber-768 encapsulation | 8,000 ops/second |
| Key storage | 2048 key slots, 256-bit keys, no external bus access |
| PUF entropy | 256-bit device root key, NIST SP 800-90B-aligned entropy source |
| Host interface (primary) | PCIe x4, Gen 3 (32 Gbps bandwidth) |
| Host interface (secondary) | SPI Mode 0/3, up to 50 MHz |
| Management interface | I2C, 400 kHz fast mode |
| Standby power | <5 μW (zeroize circuit armed) |
| Active power | <1.2 W at full crypto throughput |
| Tamper mesh | Active metal mesh, <1 ns zeroize response |
| Tamper events logged | Cryptographically signed tamper log, non-volatile |
| Package | BGA-256, 12 mm × 12 mm, 0.8 mm pitch |
| FIPS 140-3 target | Level 3 (physical security) |
| Driver support | Linux 5.15+, UEFI 2.10, Windows Server 2022+ |
PCIe-attached HSM on host servers, providing hardware-backed key operations for cloud key management service deployments. Replaces software HSM emulation and network HSM appliances with a silicon-level trust anchor co-located with workloads.
Designed for FIPS 140-3 Level 3 and PCI-HSM key custody requirements — payment processing, PIN block encryption, and digital asset custody. Silicon-native deployment co-located at the processing node eliminates the centralized failure surface of network HSM appliances.
Evaluation kits available for qualified design partners. NDA required. Full datasheet package on request.