We're a small team doing deep work on hardware security silicon. If you want to spend your days on problems that matter — at the silicon level — we'd like to talk.
We're five people in a San Jose hardware lab. No layers between you and the silicon. The problems we work on — tamper-mesh RTL, PUF characterization, FIPS 140-3 path — don't have StackOverflow answers. You'll be doing original work, and it will ship in real products.
Design and verify RTL blocks for Bastionchip security silicon: crypto engine pipeline, PUF interface logic, tamper mesh controller, and zeroize circuitry. Experience with SystemVerilog, formal verification, and physical design closure required. Familiarity with FIPS 140-3 Level 3 physical security requirements is a strong plus.
Own the security threat model for Bastionchip silicon. Drive formal attack surface analysis, side-channel countermeasure design, and certification path planning for FIPS 140-3 and Common Criteria. You'll work directly with the RTL team to translate security requirements into design constraints. Background in hardware security evaluation or applied cryptography required.
Characterize first-silicon samples from Bastionchip's initial tape-out. Design test vector suites, run crypto throughput benchmarks, measure side-channel leakage profiles, and validate tamper-response timing. You'll produce the characterization data that goes into NDA datasheets and certification submissions. Experience with ATE systems, oscilloscopes, and FPGA-based test benches required.
We don't use recruiters. Send your background and what interests you about hardware security silicon to [email protected].