Team — Bastionchip

Noam Bar-Lev

CEO & Co-Founder

Previously a principal security engineer at a major cloud hyperscaler, where Noam led the HSM infrastructure and attestation service for a large-scale key management platform serving tens of millions of encrypted objects across the US. The supply-chain compromise he investigated in 2023 became the direct motivation for Bastionchip's founding thesis.

Tal Kessler

CTO & Co-Founder

Spent eight years as a silicon security architect at an ARM TrustZone licensee, leading the design of secure enclave IP blocks for embedded SoCs in medical devices and industrial control systems. Brought the RTL design methodology and TSMC process-node expertise that enabled Bastionchip's first tape-out on schedule.

Reina Wolff

VP Research Engineering

PhD in side-channel analysis from Stanford Security Lab. Reina's dissertation characterizing masked PUF architectures under differential power analysis provided the foundational entropy reliability data that underpins Bastionchip's 99.97% across-temperature-cycling specification. She leads PUF validation protocols and the fuzzy extractor implementation.

Where we come from

Hyperscaler infrastructure, silicon IP, and academic hardware security

The founding team's backgrounds are complementary by design: Noam brings operational experience running HSM infrastructure at the scale where firmware compromise becomes a real incident category; Tal brings the RTL design methodology to build security primitives in silicon rather than software; Reina brings the academic rigor to measure PUF entropy properties against NIST standards before making specifications public. All three are based in San Jose, within the Silicon Valley semiconductor corridor, close to the foundry logistics and design ecosystem that an ASIC startup requires.

Cloud hyperscaler HSM infrastructure — key management at tens of millions of encrypted objects

ARM TrustZone silicon IP — secure enclave design for medical and industrial SoCs

Stanford Security Lab PhD — differential power analysis and masked PUF entropy characterization

San Jose, CA — Silicon Valley semiconductor corridor, TSMC tape-out and foundry logistics

Get in touch

Interested in working with the team directly?

Design partnerships are evaluated by the founding team. Reach out with your confidential compute use case and current HSM architecture.