Origin
In 2023, Noam Bar-Lev was a principal security engineer at a cloud hyperscaler when a firmware-level supply-chain compromise in a third-party HSM vendor's update pipeline exposed key material for over 60,000 customer accounts. The incident was never publicly disclosed, but it triggered an eighteen-month internal remediation effort that consumed the work of dozens of engineers.
The root cause was architecturally simple: every component of the trust chain — from the HSM firmware loader to the attestation service — ran on general-purpose processors with writeable memory. None of it had hardware-immutable identity. An attacker who could write to firmware storage could make any device claim to be any other device. The entire confidential compute stack rested on a foundation that software alone could never prove was solid.
That observation became the core insight behind Bastionchip: the cryptographic security of a data center ultimately depends on the assumption that the hardware executing key operations is the hardware it claims to be — an assumption that software alone can never prove.
First prototype
The founding team — Noam Bar-Lev, Tal Kessler (formerly leading silicon security IP at an ARM TrustZone licensee), and Reina Wolff (PhD in side-channel analysis from Stanford Security Lab) — first built a discrete PUF evaluation board on FPGA in early 2024 to validate that silicon-entropy-based identity generation could achieve NIST SP 800-90B entropy thresholds without battery backup.
The key finding from that prototype: masked PUF architectures achieved 99.97% reliability across temperature cycling. That threshold mattered — FIPS 140-3 Level 3 requires demonstrable entropy properties at manufacturing time, and the data showed that physical unclonability could replace the battery-backed key storage that made traditional HSMs mechanically complex and expensive to certify.
Where we are today
Bastionchip has taped out its first ASIC in TSMC 16nm FinFET, with engineering samples delivered to three design partners in Q1 2025 for integration testing in confidential VM workloads. We are a seed-stage company based in San Jose, operating in the Silicon Valley semiconductor corridor, and actively seeking additional design partners with FIPS 140-3 Level 3+ requirements.
Mission
Make hardware-rooted confidential compute accessible to every security-conscious infrastructure team — not just those with bespoke HSM budgets or HSM-engineering staff.
The security properties of confidential compute should not depend on which cloud provider you can afford or which certification budget your procurement team approved. Bastionchip exists to drive hardware-immutable identity down the BOM cost curve so that any operator running workloads that process sensitive data can anchor their trust chain in silicon rather than software assumptions. We focus on the foundation — the point at which a processor must prove, cryptographically and unforgeable, that it is the processor it claims to be — because everything built on top of that foundation inherits its integrity properties.
What we value
Where Bastionchip sits in the ecosystem
Bastionchip is a seed-stage silicon startup. We have taped out our first ASIC, validated the PUF architecture at temperature extremes, and are running active integration testing with design partners. We are pre-revenue and pre-scale — our focus is proving the hardware works exactly as specified before expanding the partnership program.
Interested in a design partnership?
We are selective about early integration partners. If your infrastructure requires hardware-enforced confidential compute, we want to talk.